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Clock
Signal
tT5, tT7
tT6, tT8
input setup to clock input hold from clock
Figure 64
Setup and hold time definition (single- and multi PHY)
Clock
tT9 tT10
Signal
tT11
signal going low impedance from clock signal going low impedance to clock
tT12
signal going high signal going high impedance from clock impedance to clock
Figure 65
Tri-state timing (multi-PHY, multiple devices only)
Data Sheet
257
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics Table 42 No. t1 tT2 tT3 tT4 tT5 tT6 TXDAT[7:0], TXPTY, TXSOC, TXENB TXCLAV Transmit Timing (8-Bit Data Bus, 33 MHz at Cell Interface, Single PHY) Description Limit Values Min TXCLK1) A>P TXCLK frequency (nominal) TXCLK duty cycle TXCLK peak-to-peak jitter TXCLK rise/fall time A>P Input setup to TXCLK Input hold from TXCLK 0 40 8 1 Max 33 60 5 3 MHz % % ns ns ns Unit
Signal Name DIR
tT7 tT8
1)
A

8 1
-
ns ns
The frequency should be equal or smaller than the coreclock CLOCK
Table 43 No. t1 tT2 tT3 tT4 tT5 tT6 tT7 tT8
Receive Timing (8-Bit Data Bus, 33 MHz at Cell Interface, Single PHY) Description Limit Values Min Max 33 60 5 3 MHz % % ns ns ns ns ns 0 40 8 1 8 1 Unit
Signal Name DIR RXCLK1)
A>P RXCLK frequency (nominal) RXCLK duty cycle RXCLK peak-to-peak jitter RXCLK rise/fall time
RXENB
A>P Input setup to RXCLK Input hold from RXCLK
RXDAT[7:0], A

1)
The frequency should be equal or smaller than the coreclock CLOCK
Data Sheet
258
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics Table 44 No. t1 tT2 tT3 tT4 tT5 tT6 TXDAT[7:0], TXPTY, TXSOC, TXENB, TXADR[4:0] TXCLAV Transmit Timing (8-Bit Data Bus, 33 MHz at Cell Interface, Multi-PHY) Description Limit Values Min TXCLK1) A>P TXCLK frequency (nominal) TXCLK duty cycle TXCLK peak-to-peak jitter TXCLK rise/fall time A>P Input setup to TXCLK Input hold from TXCLK 0 40 8 1 Max 33 60 5 3 MHz % % ns ns ns Unit
Signal Name DIR
tT7 tT8 tT9 tT10 tT11 tT12
1)
A

8 1 8 0 1 1
-
ns ns ns ns ns ns
The frequency should be equal or smaller than the coreclock CLOCK
Table 45 No. t1 tT2 tT3 tT4 tT5 tT6
Receive Timing (8-Bit Data Bus, 33 MHz at Cell Interface, Multi-PHY) Description Limit Values Min Max 33 60 5 3 MHz % % ns ns ns 0 40 8 1 Unit
Signal Name DIR RXCLK1)
A>P RXCLK frequency (nominal) RXCLK duty cycle RXCLK peak-to-peak jitter RXCLK rise/fall time
RXENB, RXADR[4:0]
A>P Input setup to RXCLK Input hold from RXCLK
Data Sheet
259
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics Table 45 No. tT7 tT8 tT9 tT10 tT11 tT12
1)
Receive Timing (8-Bit Data Bus, 33 MHz at Cell Interface, Multi-PHY) Description Limit Values Min Max ns ns ns ns ns ns 8 1 8 0 1 1 Unit
Signal Name DIR
RXDAT[7:0], A

The frequency should be equal or smaller than the coreclock CLOCK
9.6.4
IMA Interface
At the IMA interface the IWE8 operates in cycles of 12 system clocks. ATBTC can become active during cycle #3, the UNCHEC can become active during cycle #9. The Port number is always active for 6 cycles.
C LO C K 1 A TB T C 2 UNCHEC 3 P N 0..2
Figure 66
Timing of the IMA Interface
Data Sheet
260
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PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
Table 46 IMA Interface AC Timing Characteristics
No. 1 2 3
Parameter Min
Delay master clock to ATBTC Delay master clock to UNCHEC Delay master clock to PN[0:2]
Limit Values
Unit ns ns ns
Typ
Max
26 26 26
9.6.5
Clock Recovery Interface
CLOCK 6 SCLK 1 SSP 2 SDI B it1 B it0 3 B it3 0 1
B it3 1 4
SDOD
B it1
B it0
B it3 1 5
B it3 0
SDOR
B it1
B it0
B it3 1
B it3 0
Figure 67 Table 47 No. 1 2 3 4 5 6
Clock Recovery Interface Timing Diagram Clock Recovery Interface AC Timing Characteristics Limit Values Min Typ Max 11 ns ns ns -1 20 0 0 0 1 Unit
Parameter Delay SCLK rising to SSP Setup time SDI before SCLK rising Hold time SDI after SCLK rising Delay SCLK rising to SDOD Delay SCLK rising to SDOR Delay CLOCK to SCLK
11 11
16
ns ns ns
Data Sheet
261
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PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
9.6.6 9.6.6.1
M PADR
Microprocessor Interface Intel Mode
1 M PCS 2 M PW R 10 M PRDY 4 M PDAT 7 3 5 6 8
9
11
Figure 68 Table 48 No. 1 2 3 4 5 6 7 8 9 10 11
Intel Mode Write Cycle Timing Diagram Intel Mode Write Cycle AC Characteristics Limit Values Min Typ Max ns ns 20 ns 2 x Tclock ns 2 x Tclock 10 5 5 5 2 2 20 20 23xTclock ns ns ns ns ns ns ns 0 0 2 Unit
Parameter Setup time MPADR before MPCS low Setup time MPCS before MPWR low Delay MPRDY low after MPWR low MPDAT valid after MPWR low Pulse width MPRDY low MPRDY high to MPWR high Hold time MPDAT after MPWR high Hold time MPCS after MPWR high Hold time MPADR after MPWR high Delay MPCS low to MPRDY high Delay MPCS high to MPRDY high impedance
Data Sheet
262
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
M PADR 1 M PCS 2 M PRD 12 M PRDY 10 M PDAT 5 11 7 3 4 6 13 8 9
Figure 69 Table 49 No. 1 2 3 4 5 6 7 8 9 10 11 12 13
Intel Mode Read Cycle Timing Diagram Intel Mode Read Cycle AC Timing Characteristics
Limit Values Min Typ Max ns ns 20 ns ns ns ns ns ns 20 20 20 20 ns ns ns ns 23xTclock ns 0 0 2 2 x Tclock 10 10 3 5 5 4 5 2 2 Unit
Parameter Setup time MPADR before MPCS low Setup time MPCS before MPRD low Delay MPRDY low after MPRD low Pulse width MPRDY low MPDAT valid before MPRDY high MPRDY high to MPRD high Delay time MPDAT after MPRD high Hold time MPCS after MPRD high Hold time MPADR after MPRD high Delay MPRD low to MPDAT low impedance Delay MPRD high to MPDAT high impedance Delay MPCS low to MPRDY high Delay MPCS high to MPRDY high impedance
Data Sheet
263
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics
9.6.6.2
MPADR
Motorola Mode
1 MPCS 3 MPRW 5 MPTS 7 MPTA 12 MPDAT (READ) 16 MPDAT (WRITE) 13 8 10 9 6
2
4
11
14 15
17
Figure 70 Table 50 No. 1 2 3 4 5 6 7 8 9 10 11
Motorola Mode Timing Diagram Motorola Mode AC Timing Characteristics Limit Values Min Typ Max ns ns ns ns ns ns 15 Tclock 15 ns ns ns ns 23x Tclock ns 0 5 0 5 10 0 5 2 x Tclock Tclock 0 5 Unit
Parameter Setup time MPADR before MPCS low Hold time MPADR after MPTS high Setup time MPCS before MPTS low Hold time MPCS after MPTS high Setup time MPRW before MPTS low Hold time MPRW after MPTS high Delay MPCS low to MPTA high Delay MPTA low after MPTS low Pulse width MPTA low MPTA low to MPTS high Delay MPCS high to MPTA high impedance
Data Sheet
264
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PXB4219 / PXB4220 / PXB4221
Electrical Characteristics Table 50 No. 12 13 14 15 16 17 Motorola Mode AC Timing Characteristics (cont'd) Limit Values Min Delay MPTS low to MPDAT low impedance MPDAT valid before MPTA high Delay time MPDAT after MPTS high Delay MPTS high to MPDAT high impedance MPDAT valid after MPTS low Hold time MPDAT after MPTS high 5 1 5 2 2 17 Typ Max 15 ns ns ns ns Unit
Parameter
2 x Tclock ns ns
9.6.7
CLOCK
RAM Interface
8
Basic 12 RMCLK cycle
9
RMCLK
1
RMADR
AR1
AR2
AR3
AR4
AR5
AR6 2
AW1
AW2
AW3
AW4
AW5
AR1
RMADC
2 2
RMOE
34 5 R 2 R 3 R 4 R 5 R 6 W1 6 W2 W3 W4 W5 7
RMDAT
R 1
2
2
RMWR
2 2
RMCS
Figure 71
RAM Interface Timing Diagram
Data Sheet
265
2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics Table 51 No. 1 2 RAM Interface AC Timing Characteristics Limit Values Min Delay RMCLK rising to RMADR Delay RMCLK rising to RMADC Delay RMCLK rising to RMOE Delay RMCLK rising to RMWR Delay RMCLK rising to RMCS 3 4 5 6 7 8 9 9A Setup time RMDAT before RMCLK rising (all read cycles) Hold time RMDAT after RMCLK rising (all read cycles) Delay RMCLK falling to RMDAT low impedance (write cycle W1) Delay RMCLK rising to RMDAT (write cycles W2 to W5) Delay RMCLK falling to RMDAT high impedance (write cycle W5) Delay CLOCK to RMCLK TRMCLK: Period RMCLK FRMCLK: Frequency RMCLK 1 1 1 1 1 11 0 0 6 0 6 TCLOCK FCLOCK 8 12 8 12 Typ Max 11 7 7 7 7 ns ns ns ns ns ns ns ns ns ns ns ns MHz Unit
Parameter
9.6.8
Boundary-Scan Test Interface
1 TCK 2 TDI 4 TDO 6 TRST 5 3
Figure 72
Data Sheet
Boundary-Scan Test Interface Timing Diagram
266 2002-05-06
PXB4219 / PXB4220 / PXB4221
Electrical Characteristics Table 52 No. 1 1A 2 3 4 5 6 Boundary-Scan Test Interface AC Timing Characteristics Limit Values Min TTCK: Period TCK FTCK: Frequency TCK Setup time TMS, TDI before TCK rising 10 Hold time TMS, TDI after TCK rising Delay TCK falling to TDO valid Delay TCK falling to TDO high impedance Pulse width TRST low 10 0 0 2 x TTCK 30 30 160 6,25 Typ Max ns MHz ns ns ns ns ns Unit
Parameter
Data Sheet
267
2002-05-06
PXB4219 / PXB4220 / PXB4221
Testmode
10
10.1
31
Testmode
Device Identification Register
28 27 Partnumber(15:0) 0000000001000110B 12 11 00001000001B 1 0 1
Version(3:0) 0010B
Manufacturer-ID(10:0)
10.2
Instruction Register
The following table shows the instruction binary codes for the 4 bit instruction register. Code Boundary-Scan Instruction Register Binary Codes 0000 = EXTEST 0001 = IDCODE 0101 = SAMPLE 0101 = INTEST 0111 = CLAMP 1111 = BYPASS
10.3
Boundary-Scan Register
Table 53 describes the Boundary-Scan register. The register contains 299 cells. The cells of type "control" will disable the corresponding outputs when set. The control cells are preset to a safe logic-1 during the TEST-LOGIC-RESET state of the TAP controller. Table 53 Name ftcko_4_o ftcko_4_i ftcko_4_c ftcko_5_o ftcko_5_i ftcko_5_c rtsen_n mpcs_n
Data Sheet
Boundary Scan Register Name rxdat_2_o rxdat_3_o rxdat_4_o rxdat_5_o rxdat_6_o rxdat_7_o rxprt_o rxprt_c
268
Name ftcko_0_o ftcko_0_i ftcko_0_c frfrsn_0_o frfrsn_0_c ftdat_0_o ftdat_0_c ftmfs_0_o
2002-05-06
PXB4219 / PXB4220 / PXB4221
Testmode Table 53 Name mpwr_n mprd_n mpdat_0_o mpdat_0_i mpdat_c mpdat_1_o mpdat_1_i mpdat_2_o mpdat_2_i mpdat_3_o mpdat_3_i mpdat_4_o mpdat_4_i mpdat_5_o mpdat_5_i mpdat_6_o mpdat_6_i mpdat_7_o mpdat_7_i mpdat_8_o mpdat_8_i mpdat_9_o mpdat_9_i mpdat_10_o mpdat_10_i mpdat_11_o mpdat_11_i mpdat_12_o mpdat_12_i mpdat_13_o Boundary Scan Register (cont'd) Name rxenb_o rxenb_i rxenb_c rxclk rmclk pmt rmdat_0_o rmdat_0_i rmdat_c rmdat_1_o rmdat_1_i rmdat_2_o rmdat_2_i rmdat_3_o rmdat_3_i rmdat_4_o rmdat_4_i rmdat_5_o rmdat_5_i rmdat_6_o rmdat_6_i rmdat_7_o rmdat_7_i rmdat_8_o rmdat_8_i sdi rmdat_9_o rmdat_9_i rmdat_10_o rmdat_10_i Name ftmfs_0_c ftfrsn_0_o ftfrsn_0_c frlos_1 frclk_1 frdat_1 frmfb_1 ftcko_1_o ftcko_1_i ftcko_1_c frfrsn_1_o frfrsn_1_c ftdat_1_o ftdat_1_c ftmfs_1_o ftmfs_1_c ftfrsn_1_o ftfrsn_1_c frlos_2 frclk_2 frdat_2 frmfb_2 ftcko_2_o ftcko_2_i ftcko_2_c frfrsn_2_o frfrsn_2_c ftdat_2_o ftdat_2_c ftmfs_2_o
Data Sheet
269
2002-05-06
PXB4219 / PXB4220 / PXB4221
Testmode Table 53 Name mpdat_13_i mpdat_14_o mpdat_14_i mpdat_15_o mpdat_15_i rfclk clock reset_n mprdy_o mprdy_c pn_0 mpir1_n mpir2_n mpadr_0 mpadr_1 mpadr_2 mpadr_3 mpadr_4 mpadr_5 mpadr_6 mpadr_7 mpadr_8 mpadr_9 mpadr_10 mpadr_11 mpadr_12 mpadr_13 mpadr_14 mpadr_15 mpadr_16 Boundary Scan Register (cont'd) Name rmdat_11_o rmdat_11_i rmdat_12_o rmdat_12_i tbus rmdat_13_o rmdat_13_i sdod sdor rmdat_14_o rmdat_14_i rmdat_15_o rmdat_15_i rmdat_16_o rmdat_16_i ssp rmdat_17_o rmdat_17_i rmdat_18_o rmdat_18_i rmdat_19_o rmdat_19_i rmdat_20_o rmdat_20_i sclk rmdat_21_o rmdat_21_i rmdat_22_o rmdat_22_i rmdat_23_o Name ftmfs_2_c ftfrsn_2_o ftfrsn_2_c frlos_3 frclk_3 frdat_3 frmfb_3 ftcko_3_o ftcko_3_i ftcko_3_c frfrsn_3_o frfrsn_3_c ftdat_3_o ftdat_3_c ftmfs_3_o ftmfs_3_c ftfrsn_3_o ftfrsn_3_c frlos_4 frclk_4 frdat_4 frmfb_4 tscsh frfrsn_4_o frfrsn_4_c ftdat_4_o ftdat_4_c ftmfs_4_o ftmfs_4_c ftfrsn_4_o
Data Sheet
270
2002-05-06
PXB4219 / PXB4220 / PXB4221
Testmode Table 53 Name mpadr_17 licec clk52 e1ds1 tscen txadr_0 txadr_1 txadr_2 txadr_3 txadr_4 rxadr_0 rxadr_1 rxadr_2 rxadr_3 rxadr_4 pn_1 pn_2 txcla_i txcla_o txcla_c txenb_o txenb_i txenb_c txsoc txdat_0 txdat_1 txdat_2 txdat_3 txdat_4 txdat_5 Boundary Scan Register (cont'd) Name rmdat_23_i rmdat_24_o rmdat_24_i rmdat_25_o rmdat_25_i rmdat_26_o rmdat_26_i rmdat_27_o rmdat_27_i rmdat_28_o rmdat_28_i rmdat_29_o rmdat_29_i rmdat_30_o rmdat_30_i rmdat_31_o rmdat_31_i rmdat_32_o rmdat_32_i rmwr_n rmcs_n rmoe_n rmadc_n unchec_4 rmadr_0 rmadr_1 rmadr_2 rmadr_3 rmadr_4 rmadr_5 Name ftfrsn_4_c frlos_5 frclk_5 frdat_5 frmfb_5 frfrsn_5_o frfrsn_5_c ftdat_5_o ftdat_5_c ftmfs_5_o ftmfs_5_c ftfrsn_5_o ftfrsn_5_c frlos_6 frclk_6 frdat_6 frmfb_6 frfrsn_6_o frfrsn_6_c ftdat_6_o ftdat_6_c ftmfs_6_o ftmfs_6_c ftfrsn_6_o ftfrsn_6_c frlos_7 frclk_7 frdat_7 frmfb_7 ftcko_6_o
Data Sheet
271
2002-05-06
PXB4219 / PXB4220 / PXB4221
Testmode Table 53 Name txdat_6 txdat_7 txprt uttr_n txclk rxsoc_o rxsoc_c rxcla_o rxcla_i rxcla_c atbtc_3 rxdat_0_o rxdat_c rxdat_1_o Boundary Scan Register (cont'd) Name rmadr_6 rmadr_7 rmadr_8 rmadr_9 rmadr_10 rmadr_11 rmadr_12 rmadr_13 rmadr_14 rmadr_15 frlos_0 frclk_0 frdat_0 frmfb_0 Name ftcko_6_i ftcko_6_c ftcko_7_o ftcko_7_i ftcko_7_c frfrsn_7_o frfrsn_7_c ftdat_7_o ftdat_7_c ftmfs_7_o ftmfs_7_c ftfrsn_7_o ftfrsn_7_c
Data Sheet
272
2002-05-06
PXB4219 / PXB4220 / PXB4221
Package Outlines
11
Package Outlines
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device
Dimensions in mm
Figure 73
Package Outline: P-BGA-256 (Plastic Metric Quad Flat Package)
Data Sheet
273
2002-05-06
PXB4219 / PXB4220 / PXB4221
Appendix
12
12.1
Appendix
ATM Adaptation Layer 1
The ATM Adaptation Layer 1 (AAL1) consists of two sublayers: The Segmentation and Reassembly Sublayer (SAR), which is responsible for sequence integrity of the transmitted ATM cell stream and the Convergency Sublayer, responsible for blocking of user data into 47-octet SAR boundaries. Figure 74 gives an overview on the AAL1 frame-structure as defined in ITU-T I.363.1 [31].
Parity Pointer
1 bit 7 bit
AAL user info
N octets
Dummy Fill
P format
P
1 octet
User information
46 octets
CS-Sublayer
Non-P format
User information
47 octets
CSI
1 bit
SC
3 bit
CRC
3 bit
Py
1 bit
SAR-Sublayer SN SNP SAR-SDU
47 octets
1 octet
ATM Header
5 octets Pointer CSI
ATM-SDU = SAR-PDU
48 octets
ATM Layer
SC CRC Py SN SNP SAR SDU PDU
= octet offset of data block over 2 cells (111 1111 if not required) = Convergency Sublayer Indication Non-P Format: CSI = 0 P format: CSI = 1 if SC = 0,2,4 or 6, P-field may be inserted CSI = 0 if SC = 1,3,5 or 7, P-field is unused (Non-P format used) = Sequence Count = Cyclic Redundancy Check = Even Parity bit = Sequence Number incremented by 1 modulo 8 for each SAR-SDU = Sequence Number Protection = Segmentation & Reassembly = Service Data Unit = Protocol Data Unit
Figure 74
Structure of the AAL1 SAR-PDU
Data Sheet
274
2002-05-06
PXB4219 / PXB4220 / PXB4221
Appendix Robust Sequence Count Algorithm This algorithm is completely described in annex D of the ETSI B-ISDN AAL type 1 Specification [17] and ITU-T I.363.1 [31] and is shown in Figure Figure 75. The algorithm is described by a state machine of 5 states. A change in states within the state machine is indicated by an arrow, on which there are two distinct values represented. The first value refers to the event that originates the state change, and the second value refers to the action to be taken as a result of that event. A decision in this algorithm is taken after evaluation of 2 consecutive SN. This means that when a cell is received it must be temporarily stored, waiting for the next cell before it is finally passed to the reassembly buffer. In the state machine, an action to be taken (accept or discard) always refers to the stored cell. The sequence counting of modulo 8 permits that the algorithm detects a maximum of to 6 consecutive lost cells and 1 misinserted cell, assuming that misinsertion of one cell is at least as probable as the loss of 7 consecutive cells. Lost cells are compensated by inserting an appropriate number of dummy cells into the transmitted data of the channel. This is required to maintain bit count integrity. The number of octets inserted per dummy cell is equal to the number of user information octets in the SAR-PDU payload of each cell. When one misinserted cell is detected, the algorithm is able to delete the misinserted cell, because of the delay of one cell in taking a decision.
Data Sheet
275
2002-05-06
PXB4219 / PXB4220 / PXB4221
Appendix
invalid SN/discard
Initialization
out of seq/discard
Start
valid SN/discard invalid SN/discard
Out of Sync
out of seq/discard in seq/accept invalid SN/discard in seq - 1+1/accept in seq - 1/discard out of seq/accept in seq/accept
T1306830-95
in seq/insert dummy cell(s) + accept Sync
in seq - 1+1/accept
invalid SN/accept
in seq - 1/discard
Out of Seq
invalid SN/discard Invalid
Figure 75
Informative and Example Algorithm State Machine (Fig. III.2/I.363.1)
Data Sheet
276
2002-05-06
out of seq/discard
PXB4219 / PXB4220 / PXB4221
Appendix Fast Sequence Count Algorithm The state machines of the robust SC algorithm and the fast SC algorithm are the same. The only difference is that in the fast algorithm, the action to be taken always refers to the currently received cell, while in the standard algorithm it refers to the temporarily stored cell. Therefore the fast SC algorithm does not introduce additional one-cell delay. In the fast SC algorithm, a misinserted cell is immediately accepted in the reassembly buffer. Only at the arrival of the next cell, it is detected that the previous cell was misinserted. Because the misinserted cell was already accepted, the current (in sequence) cell will be discarded instead. Lost cells are compensated with the insertion of dummy cells as in the standard algorithm. Frequency and Value of the Pointer Field The pointer field contains the binary value of the offset, measured in octets, between the end of the pointer field and the start of the structured block, in the 93 octet payload. The payload consists of the remaining 46 octets of this SAR-PDU payload and the 47 octets of the next SAR-PDU payload. The frequency of occurrence of the pointer field is according to ITU-T I.363.1 [31]. The pointer field is used exactly once in every cycle, where a cycle is the sequence of eight consecutive SAR-PDUs with Sequence Count values 0, 1, to 7. The pointer field is used at the first available opportunity in a cycle to point to a start of a structured block. If a start of a structured block is not present in a cycle, then a pointer field containing a dummy offset value `127' is used at the last opportunity in the cycle.
Data Sheet
277
2002-05-06
PXB4219 / PXB4220 / PXB4221
Appendix
12.2
Synchronous Residual Time Stamp SRTS
This sub chapter contains a short description of the SRTS method, as defined in [12] and [31]. The SRTS algorithm is used to measure the frequency deviation of a data stream which is packetized in ATM cells. This frequency is coded in 4 bits and sent to the receiver. At the receiver, the correct frequency is regenerated. The 4 RTS bits are spread over 8 ATM cells. These 8 ATM cells contain 8 x 47 byte x 8 bit/byte = 3008 bits of data. In case of an E1 line, the data arrives with 2.048 Mbit/s, thus after 3008 bit / 2.048 Mbit/s = 1,46875 ms a complete RTS value is received. The frequency of generated RTS values is 681 Hz. The RTS value is calculated in the following way: In N = 3008 cycles of Fdata, we have Mq cycles of the reduced network clock. The reduced network clock Fnx has to fulfil the following equation: 1 <= Fnx / Fdata < 2. This defines the value of x in the equation: Fnx = 8 kHz X 19440 / 2^x. For a full E1 line Fdata = 2.048 MHz, x = 6 and Fnx = 2.43 MHz. The maximum input frequency deviation of 200 ppm (E1 lines: less than 50 ppm) of the data clock translates in a deviation from Mq. At the receiving side, the same network clock is available and the numbers N and x are known. As a result, the nominal value Mnom of Mq is known, and only the deviation from Mnom has to be transmitted. The number of bits to transmit the deviation (p = 4) has to be sufficient for the maximum frequency deviation.
tolerance N cycles T seconds fs t
Mq fnx
Mmin Mnom
Mmax
t y 2p
T1817630-92
y
Figure 76
The Concept of Synchronous Residual Time Stamp (SRTS) (Fig. 5/ I.363.1)
278 2002-05-06
Data Sheet
PXB4219 / PXB4220 / PXB4221
Appendix RTS values are generated as follows:
T
fs
Counter A divided by N
Latch
RTS
fn
1 -- x
fnx
P-bit counter Ct
T1817640-92
Figure 77
Generation of Residual Time Stamp (RTS) (Fig.6/ I.363.1)
The transformation of RTS values in a clock is not specified in the SRTS specifications. Basically (the implementation is slightly different), the ICRC calculates another RTS value based on the transmit clock. The difference between received RTS values and locally calculated RTS values, drives a DCO. This solution can be described as a PLL with an unusual phase comparator.
Data Sheet
279
2002-05-06
PXB4219 / PXB4220 / PXB4221
Appendix
12.3
Adaptive Clock Method ACM
The adaptive clock method does not require information concerning the source clock transferred over the ATM network. The speed of the transmitter is adjusted to the filling level of the receive buffer. If the transmit clock is too slow, the buffer filling level will increase causing the clock recovery circuit to slow down the transmit clock. If the transmit clock is too fast the buffer filling level will decrease. In this case the clock recovery circuit will increase the transmit clock.
Data Sheet
280
2002-05-06
PXB4219 / PXB4220 / PXB4221
Appendix
12.4
Channel Associated Signalling
ITU-T recommendation G.704 [24] defines Channel Associated Signalling (CAS) for interfaces at 2048 Kbit/s (E1) and 1544 Kbit/s (DS1) interfaces carrying 64 kbit/s channels. The mapping of E1 or DS1 multiframes containing CAS into ATM cells is defined in the ATM-Forum "Circuit Emulation Services Specification" [10]. In case of E1 and DS1 circuit emulation, the user information carried via AAL1 consists of a stream of payload substructures followed by an optional signalling substructure. Each payload and signalling substructure corresponds to one E1 multiframe / DS1 extended superframe. The payload substructure contains the channel slots and the optional signalling substructure contains the signalling bits associated with the channels. The following section gives an overview on this topic.
12.4.1
E1
An E1 multiframe comprises 16 consecutive frames. These are numbered from 0 to15. The multiframe alignement signal is 0000 and occupies digit time slots 1 to 4 of 64 kbit/ s channel time slot 16 in frame 0. When 64 kbit/s channel time slot 16 is used for channel-associated signalling, the 64 kbit/s capacity is sub-multiplexed into lower-rate signalling channels using the multiframe alignement signal as a reference. Details of the bit allocation are given in Table 54 Table 54 Bit allocation of channel associated 64 kbit/s time slot 16 for channel associated signalling Bit allocation of time slot 16 0000 abcd channel 1 abcd channel 2 ... abcd channel 15 xyxx abcd channel 16 abcd channel 17 ... abcd channel 30
E1 Multiframe Frame 0 (CasBeginFrame) Frame 1 Frame 2 ... Frame 15
x = spare bit, to be set to 1 if not used
y = Bit used for alarm indication to the remote end. In undisturbed operation, set to 0; in alarm condition, set to 1.
Data Sheet
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Appendix
.
A TM S D U of 1st ce ll
A A L1 h ead er oc tet A A L s tru ctu re po inte r = 0 tim es lot x tim es lot y tim es lot z tim es lot x tim es lot y tim es lot z
1 st fra m e
2 nd fra m e
tim es lot tim es lot tim es lot tim es lot
x y z x
1 5th fram e
1st m ultifram e
ATM SDU o f 2 nd ce ll
A A L1 h ead er oc tet tim es lot y tim es lot z A B C D tim e slot x A B C D tim es lot y A B C D tim e slot z u nus ed =0 00 0 tim es lot x tim es lot y tim es lot z
1 6th fram e s igna lling s ubs tru ctu re 1 st fra m e 2n d m ultifram e 1 4th fram e
tim es lot tim es lot tim es lot tim es lot
x y z x
Figure 78
Example Multiframe Structure for 3x64 Kbit/s E1 with CAS
12.4.2
DS1
An DS1 multiframe consists of 24 frames. They are numbered from 1 to 24. In the multiframe there are four different signalling bits (A, B, C and D) providing four independent 333 bit/s channels, two independent 667 bit/s channels or one 1333 bit/s channel. The four signalling bits for each time slot are transported in the last bit of each time slot of the frames 6, 12, 18, 24. In these frames only 7 bits are available for data transmission (Robbed Bit Signalling). When mapping DS1 Nx64 Kbit/s frames into ATM cells the CAS bits may also be transmitted in the payload section. However, only the signalling bits of the CAS substructure are relevant.
Data Sheet
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Appendix Table 55 Allocation of Channel Associated Signalling Bits to 24 Frame Multiframe Digit time slot in each channel used for Characters Signalling Frame 1 (CasBeginFrame) - Frame 5 1-8 Frame 6 Frame 7 - Frame 11 Frame 12 Frame 13 - Frame 17 Frame 18 Frame 19 - Frame 23 Frame 24 1-7 1-8 1-7 1-8 1-7 1-8 1-7 8 8 8 8 Signalling channel identifier 333 bit/s A B C D 667 bit/s A B A B 1333 bit/s A A A A
DS1 Multiframe
A A L1 h ead er oc tet A A L s tru ctu re po inte r = 0 tim es lot x tim es lot x tim es lot x
1 st fra m e 2nd fram e 3 rd fra m e 1st m ulti22 th fra m e fram e 23 th fra m e 24 th fra m e sig na lling 1 st fra m e 2nd fram e 3 rd fra m e 2n d m ultifram e 19 th fra m e 20 th fra m e 2 1st fra m e
A TM S D U A B C D ts x
tim es lot x tim es lot x tim es lot x u nus ed =0 00 0 tim es lot x tim es lot x tim es lot x
tim es lot x tim es lot x tim es lot x
Example Multiframe Structure for 1x64 Kbit/s DS1 with CAS
Data Sheet
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Contacts for SRTS Patent Fee
13
Contacts for SRTS Patent Fee
When using the PXB4220 a patent fee for the SRTS clock recovery needs to be paid to Telcordia Technologies, Inc.:
Telcordia Technologies, Inc. 331 Newman Springs Road NVC-3Z375 Red Bank, NJ 07701-5699 Web: http://www.telcordia.com
Data Sheet
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Glossary
14
AAL ACM ATM B-ISDN CBR CDV CES CLP CRC CS CSI DCO DS1 EC FALC FAM FIFO FS/DL FSM GFC GIM HEC I/O ICRC ITU ITU-T IWE8 IWECORE LCD LIC
Data Sheet
Glossary
ATM Adaptation Layer Adaptive Clock Method Asynchronous Transfer Mode Broadband - Integrated Services Digital Network Constant Bit Rate Cell Delay Variation Circuit Emulation Service Cell Loss Priority Cyclic Redundancy Check Convergence Sublayer Convergence Sublayer Indication Digitally Controlled Oscillator Digital Signal 1 (1.544 Mbit/s) (=T1) Echo Canceller Framer And Line Interface Component FALC Mode First In, First Out Buffer Frame Sync/Data Link Finite State Machine Generic Flow Control Generic Interface Mode Header Error Control Input/Output Internal Clock Recovery Circuit International Telecommunications Union International Telecommunications Union - Telecommunications Standardization Sector Interworking Element component for 8 channels PXB 4220 IWE8 without ICRC Loss of Cell Delineation Line Interface Card or Line Interface Circuit
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Glossary LOS LSB MSB NIC NNI OAM OCD PDU PHY PTI RTS SAR SARE SC SDT SN SNP SRTS SSRAM SYM TAP TBD UDT UNI UTOPIA UTOPIA Receive Interface (Upstream) UTOPIA Transmit Interface (Downstream) VC
Data Sheet
Loss of Signal Least Significant Bit Most Significant Bit Network Interface Controller or Card Network-to-Network Interface Operation, Administration, and Maintenance Out of Cell Delineation Protocol Data Unit Physical Layer Device Payload Type Identifier Residual Time Stamp Segmentation And Reassembly Segmentation And Reassembly Element, PXB 4110 Sequence Count Structured Data Transfer Sequence Number Sequence Number Protection Synchronous Residual Time Stamp Synchronous Static RAM Synchronous Mode Test Access Port To Be Defined Unstructured Data Transfer User-to-Network Interface Universal Test and Operations Physical Interface for ATM Data is transferred from the PHY Layer (in this case the IWE8) to the ATM Layer.
Data is transferred from the ATM Layer to the PHY Layer (in this case the IWE8).
Virtual Channel
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Glossary VCI VP VPI Virtual Channel Identifier Virtual Path Virtual Path Identifier
Data Sheet
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Bibliography
15
Bibliography
1. ANSI, American National Standard for Telecommunications. Digital Hierarchy Formats Specification, T1.107-1995. 2. ANSI, B-ISDN Customer Installation Interfaces: Physical Layer Specification, Draft American National Standard for Telecommunications, T1E1.2/93 020R2. 3. ANSI, B-ISDN Network Node Interfaces and Inter-Network Interfaces: Rates and Formats Specification, Draft American National Standard for Telecommunications T1S1.5/94 001R1. 4. ATM Forum, DS1 Physical Layer Specification, Version 1.0, af-phy-0016, September 1994 5. ATM Forum: UTOPIA Specification Level 1, Version 2.01, af-phy-0017.000, March 1994 6. ATM Forum: UTOPIA Level 2 Specification, Version 1.0, ATM Forum Contribution afphy-0039.000, June 1995. 7. ATM Forum, "E1 Physical Interface Specification", af-phy-0064.000, September, 1996 8. ATM Forum, Inverse Multiplexing for ATM (IMA Specification, Version 1.1, af-phy0086.001, February, 1999 9. ATM Forum, "ATM on Fractional E1/T1", str-phy-fn64-01.00, July, 1999 10.ATM Forum, Circuit Emulation Service Interoperability Specification Version 2.0, afvtoa-0078.000, January, 1997. 11.ATM Forum, "User-Network Interface Specification", Version 3.1, 1994 12.Bellcore, Generic requirement, ATM and AAL protocols, GR-1113-CORE, Issue 1, July 1994 13.Bellcore, Asynchronous Transfer Mode (ATM) and ATM Adaptation Layer (AAL) Protocols Generic Requirements, GR-1113-CORE, Issue 1, July 1994. 14.Bellcore, "Digital Cross-Connect System - Generic Requirements and Objectives", TR-NWT-000170, Issue 2, January, 1993 15.Bellcore, B-ISDN UNI and NNI Physical Layer Generic Criteria, TR-NWT-001112, Issue 1, June 1993 16.Bellcore, Transport Systems Generic Requirements, TR-TSV-000499, Issue 4, December 1991 17.ETSI, B-ISDN ATM Adaptation Layer (AAL) Specification Type 1, prI-ETS 300353, December 1994 18.ETSI, Transmission and Multiplexing (TM); Generic Frame Structures for the Transport of Various Signals (including ATM cells) at the CCITT Recommendation. G.702 Hierarchical Rates of 2048-kbit/s, 34368-kbit/s and 139264-kbit/s; prETS 300337, February 1993 19.IEEE Std 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture 20.Infineon, Data sheet: Frame and Line Interface Component (FALC), PEB 2254 21.Infineon, Prelininary Product Overview: Smart Integrated Digital Echo Canceller (SIDEC), PEB 20954
Data Sheet 288 2002-05-06
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Bibliography 22.ITU-T, Recommendation G.131, Control of talker echo, revised 1996 23.ITU-T, Recommendation G.703, Physical/Electrical Characteristics of Hierarchical Digital Interfaces, Geneva 1991 24.ITU-T, Recommendation G.704, Synchronous Frame Structures used at 1544, 6312, 2048, 8488 and 44736 kbit/s Hierarchical Levels, 07/95 25.ITU-T, Recommendation G.775, Loss of Signal and Alarm Indication Signal Defect Detection Criteria for Equipment Interfaces described in Recommendation G.703 and Operating at Bit Rates described in Recommendation G.702, COM 15-R 9-E, October 1993 26.ITU-T, Recommendation G.804, "ATM Cell Mapping into Plesiochronous Digital Hierarchy (PDH)", February 1998 27.ITU-T, Recommendation G.823, The Control of Jitter and Wander within Digital Networks which are based on the 2048-kbit/s Hierarchy, March 1993 28.ITU-T, Recommendation G.824, The Control of Jitter and Wander within Digital Networks which are based on the 1544-kbit/s Hierarchy, March 1993 29.ITU-T Recommendation I.231.10, "Circuit-mode Multiple-rate Unrestricted 8 kHz Structured Bearer Service Category" 30.ITU-T, Recommendation I.361, B-ISDN ATM Layer Specification, 11/95 31.ITU-T, Draft Recommendation I.363.1, B-ISDN ATM Adaptation Layer specification: Type 1 AAL, 08/96 32.ITU-T Recommendation I.432 "B-ISDN user-network interface - Physical layer specification", March, 1993 33.ITU-T Recommendation I.432.1 "B-ISDN user-network interface - Physical layer specification: General characteristics", August, 1996 34.ITU-T Recommendation I.432.3 "B-ISDN user-network interface - Physical layer specification: 1544 kbit/s and 2048 kbit/s operation", August, 1996
Data Sheet
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